This invention relates to low-power-dissipation pulsed-power-supply (PPS) complementary metal-oxide-semiconductor (CMOS) circuits and, more particularly, to interfacing PPS circuits with conventional CMOS circuits in a hybrid data processing system.
It is known that low-power-dissipation operation of a conventional CMOS circuit fabricated in integrated-circuit (IC) form can be achieved if the power supply lead of the circuit is ramped repetitively between VDD and VSS. During the so-called power-down phase of each ramped cycle, the state of the circuit is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called pulsed-power-supply CMOS and is characterized by a power dissipation property that is typically approximately an order of magnitude less than that of conventional CMOS. The technique is described, for example, in "Pulsed Power Supply CMOS--PPS CMOS" by T. J. Gabara, Proceedings of 1994 IEEE Symposium on Low Power Electronics., San Diego, Calif., October 10-12, 1994, pages 98-99. Further, the technique is described in T. J. Gabara's copending commonly assigned designated U.S. patent application Ser. No. 08/225,950, filed Apr. 8, 1994.
In some cases of practical importance, it is advantageous to design a hybrid data processing system that comprises an assemblage of IC chips including both conventional and PPS CMOS chips. In such a system, the data signal representations employed on the PPS chips are inherently different from those utilized on the conventional CMOS chips. Thus, to achieve communication among such dissimilar chips, some instrumentality is needed in a hybrid system to convert conventional CMOS data representations to the PPS data format, and vice versa. Without some simple and effective way of making these conversions, the advantages of incorporating PPS chips into a data processing system could not be realized.